EngineeringOn site
Package Layout Engineer - Hardware
NVIDIASanta Clara, CA
Posted Oct 13, 2026
What you’d do
Implement high speed and high density ASIC packages on a layout team, including substrate breakout patterns, package pinout optimization, routing, placement, stack-up, and power distribution. Full time role in Santa Clara, CA. Found on the employer's careers page on Oct 14, 2026. Apply through the link.
You’ll need
- Experience with Cadence APD or SiP tool suite
- ASIC package layout experience
- Package routing, placement, and stack-up skills
- Power distribution and reference plane design
- CAD library and symbol development
Our summary of the listing. The full listing has the details.