ASIC Design Verification Engineer

What you’d do

Build and maintain ASIC design verification environments for data center chips, writing test plans and running simulations to confirm designs meet coverage goals. Full time in San Jose, California. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's + 5 yrs ASIC experience, or Master's + 3 yrs, or PhD
• SystemVerilog and UVM methodology
• Building reusable, scalable test benches from scratch
• Scripting in Perl and/or Python
• Gate level simulation on netlists