EngineeringOn site
Design Verification Engineer (Silicon Engineering)
SpaceXPalo Alto, CA
$135,000–155,000/yr (Level I); $155,000–210,000/yr (Level II)
Posted Jul 14, 2026
What you’d do
Verify digital ASICs at block and system level for Starlink chips, writing test plans, building SystemVerilog testbenches, running regressions, and automating tests with Python and MATLAB. Extended hours and weekends may be needed to meet milestones. Found on the employer's careers page on Sep 27, 2026. Apply through the link.
Our summary of the listing. The full listing has the details.