EngineeringInternshipOn site
Design Engineering Intern (CCE2)
Astera LabsSan Jose, CA
$35–55/hr plus $500/week housing stipend
Posted Sep 7, 2026
What you’d do
Interns develop digital logic for advanced connectivity ASICs, working on RTL, simulation, synthesis, verification, and related tasks in a design engineering team. The role involves debugging and implementing hardware based on product requirements. Found on the employer's careers page on Oct 22, 2026. Apply through the link.
You’ll need
- Internship experience
- Knowledge of RTL and digital logic design
- Familiarity with ASIC design flow
- Ability to debug hardware behavior
- On-site work in San Jose, CA
Our summary of the listing. The full listing has the details.