Senior Mask Design Engineer - Hardware

What you’d do

Perform physical layout for mixed-signal functions such as PLLs, high-speed SerDes, ADCs, and ESD structures in sub-micron CMOS using Cadence tools. Work with ASIC and mixed-signal engineers on floor planning, custom layout, and design rule and schematic verification. Full time. Found on the employer's careers page on Sep 29, 2026. Apply through the link.