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RTL2GDS IC Sr. Principal Design Engineer

CadenceSan Jose, CA

$161,000–299,000/yr

Posted Sep 23, 2026

What you’d do

Provide pre- and post-sales technical support to Cadence customers on digital implementation and signoff, including synthesis, place and route, design closure, and timing/power signoff. Guide customers, run benchmarks and demos, and work with R&D on tool improvements. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

  • BS, MS, or PhD in EE
  • 10–12 years industry experience in design and EDA
  • ASIC design implementation knowledge
  • Hands-on Place & Route experience (Innovus, ICC2, Fusion Compiler)
  • Digital implementation and signoff expertise

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