Senior Mask Layout Design Engineer

What you’d do

Perform physical layout for mixed-signal functions such as PLLs, high-speed I/O, general I/O, and ESD structures in sub-micron CMOS technologies using Cadence tools. Work with ASIC and mixed-signal engineers on floor planning, custom layout, and verification against design rules and schematics. Full time. Found on the employer's careers page on Oct 6, 2026. Apply through the link.

You’ll need

• Physical layout for mixed-signal circuits
• Cadence layout tools
• Sub-micron CMOS technology experience
• Design rule and schematic verification
• Floor planning and custom layout