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Principal Engineer - Standard Cell Design

IntelSanta Clara, CA

$220,920–311,890/yr

Posted Jul 14, 2026

What you’d do

Lead standard cell library strategy and circuit design for high-performance, low-voltage silicon, including sequential and clocking circuits and PPA/Vmin optimization across advanced nodes. Full time in Santa Clara, California. Found on the employer's careers page on Sep 29, 2026. Apply through the link.

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