Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

What you’d do

Own full-chip physical verification for advanced-node silicon, running DRC, LVS, ESD, PERC and antenna signoff in Calibre, ICV or Pegasus. Coordinate tapeout signoff with block, top-level and foundry teams; extended hours and weekends may be needed. Found on the employer's careers page on Sep 27, 2026. Apply through the link.