FPGA Design Engineer

What you’d do

Develop RTL for Xilinx FPGA and Lattice CPLD designs, including simulation, synthesis and timing validation in Verilog, plus IP creation and board bring-up support. Full time in Spring, Texas. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in Electrical Engineering
• 4+ years writing RTL for FPGAs
• Verilog RTL simulation and synthesis
• Xilinx (AMD) FPGA and/or Lattice CPLD experience
• Experience with complex compute boards and/or ASIC designs