Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

What you’d do

Develop and maintain block and full-chip static timing analysis flows, write and validate timing constraints, run STA, and advise engineers on fixing timing issues. Full-time role on the Annapurna Labs team in Cupertino, California. Found on the employer's careers page on Oct 8, 2026. Apply through the link.

You’ll need

• BS + 8yrs, MS + 6yrs, or PhD + 4yrs in EE/CS
• 3+ years of Static Timing Analysis
• 3+ years of timing constraint development
• Expertise in timing analysis fundamentals
• EDA timing tools such as PrimeTime or Tempus