Principal Design Engineer

What you’d do

Lead verification strategy and testbench architecture for customer ASIC projects, writing SystemVerilog/UVM test cases and debugging complex design bugs with design engineers. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related
• 8–10 years hands-on DV experience in semiconductor/ASIC/SoC
• Expertise in SystemVerilog and UVM
• Understanding of RTL, timing, clocking, resets
• Customer interaction and technical leadership