Senior ASIC Physical Design Engineer

What you’d do

Perform static timing analysis, create and maintain timing constraints and budgets, and drive timing closure for partition-level and full-chip ASIC designs. Collaborate with design, DFT, and signal integrity teams on implementation flows and methodologies. Full time. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• ASIC physical design experience
• Static timing analysis for hierarchical designs
• Timing constraints and timing budgets
• Full-chip timing closure
• ASIC implementation flows and automation