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Mask Design Engineer – Hardware

NVIDIASanta Clara, CA

Posted Oct 13, 2026

What you’d do

Perform physical layout for silicon interposers using Cadence tools and run design feasibility studies on package size, cost, and performance. Work with package technical leads and I/O signal integrity engineers to deliver product packages on a tight schedule. Full time. Found on the employer's careers page on Oct 13, 2026. Apply through the link.

You’ll need

  • Physical layout for silicon interposer
  • Cadence layout tools
  • Custom layout and verification against design rules and netlists
  • Cross-functional collaboration with package and signal integrity engineers

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