Principal Verification Engineer

What you’d do

Design and implement verification test bench infrastructure and test cases for system, chip and block level verification using SystemVerilog libraries such as OVM, UVM and VMM. Develop functional test and verification plans and work with the VLSI design team on verification strategy. Full-time. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• 10+ years relevant experience with BS, or 8+ with MS
• BS in Computer Science, Electrical Engineering, Computer Engineering or related
• SystemVerilog class libraries (OVM, UVM, VMM)
• Pseudo-random and functional coverage verification methodologies
• Functional test and verification plan development