Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging

What you’d do

Design and verify advanced semiconductor package layouts, including die floor planning, bump assignment, RDL routing, substrate design, and tape out. Work on 2.5D interposer, 3D-IC, and fan-out wafer-level packaging. Full-time in Tempe, Arizona. Found on the employer's careers page on Sep 30, 2026. Apply through the link.