CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)

What you’d do

Design and verify RISC-V CPU microarchitecture and SystemVerilog RTL, develop verification tests, run simulations, debug failures, and collaborate with teams. Full-time role in Austin, Texas for new graduates in electrical or computer engineering. Found on the employer's careers page on Oct 23, 2026. Apply through the link.

You’ll need

• Bachelor's, Master's, or PhD in Electrical or Computer Engineering
• Minimum 3.0 GPA
• English fluency written and verbal
• Experience with SystemVerilog and CPU microarchitecture
• Full-time position in Austin, Texas