Sr. Physical Design Verification Engineer, Annapurna Labs

What you’d do

Drive full chip floorplan, integration, and physical verification sign-off, running DRC, LVS, and PERC checks with Calibre and IC Validator. Full-time role in Austin, Texas, also involving foundry interface and mentoring junior engineers. Found on the employer's careers page on Sep 30, 2026. Apply through the link.