ASIC DFT Technical Leader

What you’d do

Lead DFT work on next-generation networking chips in Cisco's Silicon One organization, partnering with front-end RTL and backend physical design teams to define test requirements early and carry DFT and quality through implementation and post-silicon validation. Full time in San Jose, California. Found on the employer's careers page on Oct 19, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in Electrical or Computer Engineering
• 10+ years of experience
• DFT, test and silicon engineering experience
• JTAG protocols, Scan and BIST architectures
• Memory BIST and boundary scan