Principal ASIC Design Engineer (Starshield)

What you’d do

Design digital ASICs and FPGAs for Starshield national security programs, defining micro-architecture, implementing RTL in Verilog/SystemVerilog, and supporting timing closure and silicon bring-up. Requires a bachelor's degree and 8+ years of RTL or FPGA/ASIC experience; may involve long hours, weekend work, and travel for off-site testing. Found on the employer's careers page on Sep 27, 2026. Apply through the link.