ASIC Physical Design Principal Engineer

What you’d do

Design and implement fullchip floorplans and RTL-to-GDSII flows for ASICs, focusing on performance, power, and die size optimization. Collaborate with system and package teams and improve design methodologies. Full-time in San Jose, CA. Found on the employer's careers page on Oct 23, 2026. Apply through the link.

You’ll need

• Bachelor's degree in Engineering and 15+ years ASIC experience or Master's with 12+ years or PhD wit
• Experience with RTL2GDSII flow and 7nm/5nm/3nm or below process technologies
• Proficiency in low-power design methodologies using UPF
• Experience with fullchip floorplan, clock mesh, Flex-HTree methods
• Full-time schedule