ASIC Physical Design Engineer II (Full Time) - United States

What you’d do

Own RTL-to-GDSII implementation for advanced semiconductor nodes, including floor planning, place and route, clock and power distribution, and timing convergence. Perform static timing analysis and sign-offs, build automation scripts, and drive timing ECO strategies with RTL, DFT, and EDA teams. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Master's degree with 0 years experience, or Bachelor's with 2 years
• Degree completed within past 3 years or within next 12 months
• RTL-to-GDSII implementation experience
• Static timing analysis (STA) and sign-off
• PrimeTime and timing ECO tools