ASIC Design Verification Technical Leader

What you’d do

Lead ASIC verification for complex networking SoCs, setting verification strategy, testplans, coverage closure, and scalable SystemVerilog/UVM environments. Mentor verification engineers and drive debug across simulation, emulation, and silicon. Full time in San Jose, California. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's with 10+ years related experience, or Master's with 7+, or PhD with 5+
• SystemVerilog
• UVM and modern verification methodologies
• Hardware emulation experience
• ASIC verification leadership