Senior ASIC Design Engineer - Memory Subsystem

What you’d do

Design and micro-architect memory subsystem components, including RTL design, synthesis, and timing analysis, while collaborating with architecture, verification, and physical design teams. Full time role based in Santa Clara, CA. Found on the employer's careers page on Oct 14, 2026. Apply through the link.

You’ll need

• ASIC design experience
• RTL design
• Synthesis and timing analysis
• Micro-architecture skills
• CAD tools