Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

What you’d do

Own full-chip physical verification for advanced-node silicon, running DRC, LVS, ESD, PERC and antenna signoff in Calibre, ICV or Pegasus, and developing and optimizing verification flows. Involves debugging violations, coordinating tapeout signoff, and working with foundry teams; extended hours and weekends as needed. Found on the employer's careers page on Sep 27, 2026. Apply through the link.