ASIC Design Verification Engineer

What you’d do

Lead ASIC verification strategy and methodology across multiple programs and product lines, architect reusable verification infrastructure, and mentor verification teams. Full time in San Jose, California. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's + 7 years related experience, or Master's + 4, or PhD + 1
• SystemVerilog and UVM experience
• Verification methodology experience
• Architecting verification strategies for complex ASIC programs
• Leading verification teams or projects