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Principal Design Engineer

CadenceSan Jose, CA

$140,000–260,000/yr

Posted Sep 28, 2026

What you’d do

Join a team developing high-speed wireline communications transceivers in CMOS silicon. The role focuses on numerical modeling and architecture, guiding selection and specification of transceiver components through mathematical and computer modeling, and collaborating with analog, digital, and applications engineers on design tradeoffs. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

  • Numerical modeling and architecture experience
  • Mathematical and computer modeling techniques
  • High-speed wireline transceiver design
  • CMOS silicon background
  • Collaboration with cross-functional design teams

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