Engineer II - Digital ASIC Design

What you’d do

Implement RTL in System Verilog for complex digital IP blocks, driving power, performance and area trade-offs and working with SoC integration and physical design teams. Full time; requires 2.5 to 5 years of ASIC or FPGA digital design experience. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• BS in Electrical Engineering
• 2.5–5 years ASIC or FPGA digital design experience
• System Verilog proficiency
• Cadence/Synopsys front-end EDA flow (VCS, SpyGlass, Design Compiler, PrimeTime)
• Synchronous/asynchronous design knowledge