EngineeringOn site
Principal Validation Lead
MarvellSanta Clara, CA
Posted Oct 13, 2026
What you’d do
Lead lab validation strategy and execution for advanced ASIC/SoC products with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. Combines hands-on silicon bring-up and debug with technical leadership of test planning and methodology across design, DFT, firmware, and product engineering. Full time. Found on the employer's careers page on Oct 20, 2026. Apply through the link.
You’ll need
- Bachelor's in CS, Electrical Engineering or related
- 10-15 years related experience (or Master's/PhD with 5-10 years)
- ASIC/SoC validation experience
- Silicon bring-up and debug
- CXL 3.x, HBM, DDR, PCIe, high-speed SerDes
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