ASIC DFT DV Technical Leader (Hybrid)

What you’d do

Lead DFT verification for silicon devices in Cisco's Silicon One organization, planning tests and building SystemVerilog testbenches to validate design-for-test architecture. Full-time hybrid role in San Jose, CA, collaborating with RTL and physical design teams. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• Bachelor's + 8 yrs, Master's + 6 yrs, or PhD + 3 yrs experience
• Test planning from complex design specifications
• Testbench development using SystemVerilog
• Debugging with DVE/Verdi
• TCL, Python or Perl